Projects
Technical Projects:
- Iterative decoding algorithms on modern codes| [Report] (Jan ‘20- May ‘20)
Guide: Prof. Manoj Gopalkrishnan, Prof. Nikhil Karamchandani, EE, IIT-B
Introduction: The goal in this project was to do an existing literature survey on modern codes specifically to do with LPDC (Low Density Parity Check) codes and turbo codes.- Studied the classical message passing algorithm on non-cyclic codes and the convergence in error probability of belief propagation algorithm on certain ensembles of LDPC codes under certain symmetric channels.
- Read up on EXIT charts to get an information theoretic viewpoint of the decoding process and went through the convergence of the peeling decoder of LDPC codes under Binary erasure channel.
- Studied turbo codes, their representations as factor graphs , the density evolution process during iterative decoding , stability condition, their corresponding EXIT charts and their weight distribution.
- Studied the classical message passing algorithm on non-cyclic codes and the convergence in error probability of belief propagation algorithm on certain ensembles of LDPC codes under certain symmetric channels.
- Hardware Accelerator for Graphics Computation| [Report] (Oct ‘19 - Nov ‘19)
Guide: Prof. Madhav Desai, EE, IIT-B
Introduction: The goal in this project was to build an efficient hardware accelerator which exploits parallelism.- Implemented a pipelined design for convolving a kernel with an image stored in a shared memory.
- Parallelized the operation using multiple engines which can fetch the image through pipes and perform convolution to reduce computation time and utilize the entire memory bandwidth.
- Implemented a pipelined design for convolving a kernel with an image stored in a shared memory.
- Carry Save Adder Network Optimisations| Summer Internship (May ‘19 - July’19)
Texas Instruments, Bangalore- Devised algorithms for connections of input and output pins of full adder cells so as to minimise the maximum delay of the whole network.
- Worked on buffer insertion problem and used linear programming to insert buffers so that the whole network could be wave-pipelined.
- Worked on cell-selection problem to meet a certain delay target of the whole network with the lowest cost.
- Implemented all the above algorithms using actual delay data of cells as per 65nm node technology to incorporate slew and loading of cells and generalised the above two algorithms to any combinational network.
- Devised algorithms for connections of input and output pins of full adder cells so as to minimise the maximum delay of the whole network.
- Superscaler and Pipelined Processor Design (Oct ‘18 - May ‘19)
Guide: Prof. Virendra Singh, EE, IIT-B
Introduction: The goal in this project was to implement general purpose micro-processor designs with an instruction set architecture having 16 diverse instructions in VHDL.- Pipelined RISC processor implementation (Oct ‘18 - Nov ‘18)
Employed hazard-mitigation, operand-forwarding techniques to design a six stage execution pipeline and synthesized on Altera Deo-Nano FPGA Board running at 50 MHz. - Superscaler processor implementation (Apr ‘19 - May ‘19)
Designed an out of order execution engine consisting of two way fetch supported by specialised execution engines, reorder buffer, register renaming and reservation station to extract instruction level parallelism.
- Pipelined RISC processor implementation (Oct ‘18 - Nov ‘18)
- IIT Bombay Racing (Electric Subsystem) (Academic year ‘17-‘19)
A cross functional team of 60+ students from 7 engineering disciplines which designs and fabricates an electric race car for Formula Student competition held annually at Silverstone, UK.- Designed the harness of the whole car keeping into considerations the current and voltage rating of each input signal in each board.
- Designed and tested the CAN (Controlled Area Network) node using CAN enabled micro-controller atmega-16M1 in embedded C using interrupts for sending and receiving messages.
- Developed codes using interrupts in ECU (embedded C programming) for reading data from CAN bus, processing and sending control commands to BLDC (Brushless DC motors) on CAN bus.
- Designed the harness of the whole car keeping into considerations the current and voltage rating of each input signal in each board.
- Stereo-Camera Calibration & Image Rectification on FPGA (Summer ‘18)
Guide: Prof. Sachin Patkar, EE, IIT-B- Developed a dual OV7670 camera setup compatible with De0-Nano Board (Cyclone IV-E FPGA).
- Used FTDI chip FT245RL for sending bytes captured by camera in default YUV format through serial port communication with PC by writing VHDL and Verilog codes.
- Used OpenCV library on C++ for image construction from the received bytes on the serial port of PC.
- Developed a dual OV7670 camera setup compatible with De0-Nano Board (Cyclone IV-E FPGA).